1. Field of the Invention
This invention relates to a semiconductor device and, more specifically, to the presence of an insulation layer which later functions to mask when impurities are implanted to the semiconductor device.
2. Description of the Prior Art
Recently, Bi-CMOS type ICs which include both a bipolar type transistor and a CMOS type transistor formed on one chip are available on the market. FIG. 1 shows a sectional side elevation of the Bi-CMOS type IC 2.
As shown in FIG. 1, in the Bi-CMOS type IC 2, a PNP type transistor 4 which is a part of the bipolar type transistor and a PMOS type transistor 6 which is a part of the CMOS type transistor are formed with a field oxide layer between.
In a conventional method for manufacturing the Bi-CMOS type IC 2, at first, a buried layer 12, an epitaxial layer 14, an oxide layer 16 and the field oxide layer 8 are formed on a positive type semiconductor substrate 10 in the order as shown in FIG. 2. Secondly, a gate electrode 18, an emitter/collector 20, a source/drain region 22 and a metal electrode 24 are formed consecutively as shown in FIG. 1.
By forming these parts in the above order, it is possible to form both the bipolar type transistor and the CMOS type transistor on one chip.
However, the conventional method for manufacturing the Bi-CMOS type IC 2 described above has the following problems to resolve. It is necessary to carry out implantation of boron B into a device formation region 6a of the PMOS type transistor 6 as a channel ion to adjust a threshold value of the PMOS type transistor 6, after forming the field oxide layer 8 and before forming the gate electrode 18 (see FIG. 1) as shown in FIG. 2.
Since the device formation region 6a of the PMOS type transistor 6 is the only part requiring implantation of boron B, other regions except the device formation region 6a are masked with a photo resist layer 26. Therefore, there is a limitation that the masking process for forming the photo resist layer 26 must be carried out after forming the field oxide layer 8 and before carrying out implantation of boron B as a channel ion.
Meanwhile, the impurity concentration for other regions excluding an active base formation region 4a formed between the emitter/collector 20 of the PNP type transistor 4 is adjustable for processes carried out later even when boron B is implanted into other regions. Therefore, it is not necessary to mask the regions for implantation of boron B except for the active base formation region 4a.
However, adjustment of the impurity concentration is not possible to conduct during processes carried out later. On the other hand, there are some problems with the processes to be carried out later when boron B is implanted to the active base formation region 4a.
Consequently, it is necessary to carry out the masking process which forms the photo resist layer 26 to prevent the active base formation region 4a from implantation of boron B, even though the area of the active base formation region 4a is relatively small.
Further, since the Bi-CMOS type IS 2 includes both of the bipolar transistor and the CMOS type transistor, when adjustment of operation characteristics for the Bi-CMOS type IC 2 is carried out by implanting impurities to the CMOS type transistor, the bipolar transistor must be masked. Alternatively, the CMOS type transistor must be masked when implantation of boron is carried out to the bipolar type transistor. Therefore, a great number of masking processes must be carried out during the manufacturing processes for the Bi-CMOS IC 2. It becomes a problem to carry out such masking processes.